View MB15E07PFV1_6536709.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

ds04-21343-1e fujitsu semiconductor data sheet assp single serial input pll frequency synthesizer on-chip 2.5 ghz prescaler mb15e07 n description the fujitsu mb15e07 is serial input phase locked loop (pll) frequency synthesizer with a 2.5 ghz prescaler. a 32/33 or a 64/65 can be selected for the prescaler that enables pulse swallow operation. the latest bicmos process technology is used, resuitantly a supply current is limited as low as 8 ma typ. this operates with a supply voltage of 3.0 v (typ.) furthermore, a super charger circuit is included to get a fast tuning as well as low noise performance. as a result of this, mb15e07 is ideally suitable for digital mobile communications, such as gsm (global system for mobile communications). n features high frequency operation: 2.5 ghz max (@ p= 64/65) 1.8 ghz max (@p = 32/33) low power supply voltage: v cc = 2.7 to 3.6 v very low power supply current : i cc = 8.0 ma typ. (v cc = 3 v) power saving function : i ps = 0.1 m a typ. pulse swallow function: 32/33 or 64/65 serial input 14-bit programmable reference divider: r = 5 to 16,383 serial input 18-bit programmable divider consisting of: - binary 7-bit swallow counter: 0 to 127 - binary 11-bit programmable counter: 5 to 2,047 wide operating temperature: ta = ?0 to 85 c plastic 16-pin ssop package (fpt-16p-m05) n package 16-pin, plastic ssop (fpt-16p-m05)
2 mb15e07 n pin assignment oscin oscout vp v cc do gnd xfin fin 1 2 3 4 5 6 7 8 f r f p ld/fout zc ps le data clock 16 15 14 13 12 11 10 9 (top view)
3 mb15e07 n pin descriptions pin no. pin name i/o descriptions 1 osc in i programmable reference divider input. oscillator input. connection for an crystal or a tcxo. tcxo should be connected with a coupling capacitor. 2 osc out o oscillator output. connection for an external crystal. 3v p power supply voltage input for the charge pump. 4v cc power supply voltage input. 5d o o charge pump output. phase of the charge pump can be reversed by fc bit. 6 gnd ground. 7 xfin i prescaler complementary input, and should be grounded via a capacitor. 8 fin i prescaler input. connection with an external vco should be done with ac coupling. 9 clock i clock input for the 19-bit shift register. data is shifted into the shift register on the rising edge of the clock. (open is prohibited.) 10 data i serial data input using binary code. the last bit of the data is a control bit. (open is prohibited.) control bit = ? ;data is transmitted to the programmable reference counter. control bit = ? ;data is transmitted to the programmable counter. 11 le i load enable signal input (open is prohibited.) when le is high, the data in the shift register is transferred to a latch, according to the control bit in the serial data. 12 ps i power saving mode control. this pin must be set at ? at power-on. (open is prohibited.) ps = ? ; normal mode ps = ? ; power saving mode 13 zc i forced high-impedance control for the charge pump (with internal pull up resistor.) zc = ? ; normal do output. zc = ? ; do becomes high impedance. 14 ld/fout o lock detect signal output(ld)/phase comparator monitoring output (fout). the output signal is selected by lds bit in the serial data. lds = ? ; outputs fout (fr/fp monitoring output) lds = ? ; outputs ld (? at locking, ? at unlocking.) 15 f po phase comparator output for an external charge pump. nch open drain output. 16 f r o phase comparator output for an external charge pump. cmos output.
4 mb15e07 n block diagram oscin osc out vp v cc crystal oscillator circuit 17-bit latch programmable reference divider binary 14-bit reference counter charge pump ld/fout data 19-bit shift register 19-bit shift register 7-bit latch 18-bit latch 11-bit latch binary 7-bit swallow counter programmable divider binary 11-bit programma- ble counter 1 2 3 do 5 gnd xf in clock 10 le 11 ps 12 14 9 6 4 phase comparator f p f r 16 prescaler 32/33, 64/65 super charger le sw md fp fp fp fr fr ld/fr/fp selector intermittent mode control (power save) le f in ld lock detector sw c n t 1-bit control latch 14-bit latch 3-bit latch lds fc zc 13 control circuit 15 8 7
5 mb15e07 n absolute maximum ratings note: permanent device damage may occur if the above absolute maximum ratings are exceeded. functional operation should be restricted to the conditions as detailed in the operational sections of this data sheet. exposure to absolute maximum rating conditions for extended periods may affect device reliability. n recommended operating conditions handling precautions this device should be transported and stores in anti-static containers. this is a static-sensitive device; take proper anti-esd precautions. ensure that personnel and equipment are properly grounded. cover workbenches with grounded conductive mats. always turn the power supply off before inserting or removing the device from its socket. protect leads with a conductive sheet when handling or transporting pc boards with devices. parameter symbol rating unit remark power supply voltage v cc ?.5 to +4.0 v v p v cc to +6.0 v input voltage v i ?.5 to v cc +0.5 v output voltage v o ?.5 to v cc +0.5 v storage temperature t stg ?5 to +125 c parameter symbol value unit remark min. typ. max. power supply voltage v cc 2.7 3.0 3.6 v v p v cc 6.0 v input voltage v i gnd v cc v operating temperature ta ?0 +85 c
6 mb15e07 n electrical characteristics (v cc = 2.7 to 3.6 v, ta = ?0 to +85 c) *1: conditions; v cc = 3.0 v, ta = 25 c, in locking state. parameter symbol condition value unit min. typ. max. power supply current* 1 i cc ? = 1800 mhz, fosc = 12 mhz, p = 32/33 8.0 ma power saving current ips zc = ? or open 0.1 10 m a operating frequency fin p = 32/33 100 1800 mhz p = 64/65 100 2500 mhz crystal oscillator operating frequency f osc min. 500 mvp-p 3 40 mhz input sensitivity ? vfin 50 w system (refer to the test circuit.) ?0 +2 dbm oscin v osc 500 v cc mvp-p input voltage data, clock, le, ps, zc v ih vcc 0.7 v v il vcc 0.3 input current data, clock, le, ps i ih ?.0 +1.0 m a i il ?.0 +1.0 zc i ih ?.0 +1.0 m a i il pull up input ?00 0 oscin i ih 0 +100 m a i il ?00 0 output voltage f pv ol open drain output 0.4 v f r, ld/fout v oh vcc ? 0.4 v v ol 0.4 do v doh vp ? 0.4 v v dol 0.4 high impedance cutoff current do i off 1.1 m a output current f pi ol open drain output 1.0 ma f r, ld/fout i oh ?.0 ma i ol 1.0 do i doh v cc = 3.0 v, vp = 5 v, v doh = 4.0 v, ta = 25 c ?0.0 ma i dol v cc = 3.0 v, vp = 5 v, v dol = 1.0 v, ta = 25 c 10.0
7 mb15e07 n function descriptions pulse swallow function the divide ratio can be calculated using the following equation: f vco = [(p x n) + a] x f osc ? r (a < n) f vco : output frequency of external voltage controlled oscillator (vco) n : preset divide ratio of binary 11-bit programmable counter (5 to 2,047) a : preset divide ratio of binary 7-bit swallow counter (0 a 127) f osc : output frequency of the reference frequency oscillator r : preset divide ratio of binary 14-bit programmable reference counter (5 to 16,383) p : preset divide ratio of modules prescaler (32 or 64) serial data input serial data is processed using the data, clock, and le pins. serial data controls the programmable reference divider and the programmable divider separately. binary serial data is entered through the data pin. one bit of data is shifted into the shift register on the rising edge of the clock. when the load enable pin is high, stored data is latched according to the control bit data as follows: table.1 control bit shift register con?uration control bit (cnt) destination of serial data h 17 bit latch (for the programmable reference divider) l 18 bit latch (for the programmable divider) 1 c n t 2 r 1 3 r 2 4 r 3 5 r 4 6 r 5 7 r 6 8 r 7 9 r 8 10 r 9 11 r 10 12 r 11 13 r 12 14 r 13 15 r 14 16 sw 17 fc 18 lds msb data flow lsb programmable reference counter cnt r1 to r14 sw fc lds note : start data input with msb first [table. 1] [table. 2] [table. 5] [table. 7] [table. 6] : control bit : divide ratio setting bit for the programmable reference counter (5 to 16,383) : divide ratio setting bit for the prescaler (32/33 or 64/65) : phase control bit for the phase comparator : ld/fout signal select bit
8 mb15e07 table2. binary 14-bit programmable reference counter data setting note: divide ratio less than 5 is prohibited. table.3 binary 11-bit programmable counter data setting note: divide ratio less than 5 is prohibited. divide ratio (n) range = 5 to 2,047 divide ratio (r) r 14 r 13 r 12 r 11 r 10 r 9 r 8 r 7 r 6 r 5 r 4 r 3 r 2 r 1 5 00000000000101 6 00000000000110 16383 11111111111111 divide ratio (n) n 11 n 10 n 9 n 8 n 7 n 6 n 5 n 4 n 3 n 2 n 1 5 00000000101 6 00000000110 2047 11111111111 1 c n t 2 a 1 3 a 2 4 a 3 5 a 4 6 a 5 7 a 6 8 a 7 9 n 1 10 n 2 11 n 3 12 n 4 13 n 5 14 n 6 15 n 7 n 8 n 9 n 10 n 11 16 17 18 19 msb data flow lsb programmable reference counter cnt n1 to n11 a1 to a7 note : start data input with msb first [table. 1] [table. 2] [table. 4] : control bit : divide ratio setting bits for the programmable counter (5 to 2,047) : divide ratio setting bits for the swallow counter (0 to 127)
9 mb15e07 table.4 binary 7-bit swallow counter data setting note: divide ratio (a) range = 0 to 127 table. 5 prescaler data setting table. 6 ld/fout output select data setting relation between the fc input and phase characteristics the fc bit changes the phase characteristics of the phase comparator. both the internal charge pump output level (d o ) and the phase comparator output ( f r, f p) are reversed according to the fc bit. also, the monitor pin (f out ) output is controlled by the fc bit. the relationship between the fc bit and each of d o , f r, and f p is shown below. table. 7 fc bit data setting (lds = ?? * : high impedance divide ratio (a) a 7 a 6 a 5 a 4 a 3 a 2 a 1 0 0000000 1 0000001 127 1111111 sw prescaler divide ratio h 32/33 l 64/65 lds ld/fout output signal h fout signal l ld signal fc = high fc = low do f r f p ld/fout do f r f p ld/fout f r > f p h l l (fr) l h z* (fp) f r < f p l h z* (fr) h l l (fp) f r = f p z* l z* (fr) z* l z* (fp)
10 mb15e07 when designing a synthesizer, the fc pin setting depends on the vco and lpf characteristics. power saving mode (intermittent mode control circuit) setting a ps pin to low, the ic enters into power saving mode resultatly current sonsumption can be limited to 10 m a (max.). setting ps pin to high, power saving mode is released so that the ic works normally. in addition, the intermittent operation control circuit is included which helps smooth start up from the power saving mode. in general, the power consumption can be saved by the intermittent operation that powering down or waking up the synthesizer. such case, if the pll is powered up uncontrolled, the resulting phase comparator output signal is unpredictable due to an unde?ed phase relation between reference frequency (f r ) and comparison frequency (f p ) and may in the worst case take longer time for lock up of the loop. to prevent this, the intermittent operation control circuit enforces a limited error signal output of the phase detector during power up, thus keeping the loop locked. during the power saving mode, the corresponding section except for indispensable circuit for the power saving function stops working, then current consumption is reduced to 10 m a (max.). at that time, the do and ld become the same state as when a loop is locking. that is, the do becomes high impedance. a vco control voltage is naturally kept at the locking voltage which de?ed by a lpf? time constant. as a result of this, vcos frequency is kept at the locking frequency. note: while the power saving mode is executed, zc pin should be set at ? or open. if zc is set at ? during power saving mode, approximately 10 m a current ?ws. ps pin must be set ? at power-on. the power saving mode can be released (ps : l ? h) 1 m s later after power supply remains stable. during the power saving mode, it is possible to input the serial data. table.8 ps pin setting table.9 zc pin setting ps pin status h normal mode l power saving mode zc pin do output h normal output l high impedance * : when the lpf and vco characteristics are similar to , set fc bit high. * : when the vco characteristics are similar to , set fc bit low. pll lpf vco vco output frequency lpf input voltage
11 mb15e07 n serial data input timing msb lsb data clock le t1 t4 t5 t3 on rising edge of the clock, one bit of the data is transferred into the shift register. parameter unit max. typ. min. t1 t2 t3 t4 ns ns ns ns 20 20 30 30 100 20 100 t5 t6 t7 ns ns ns t6 t7 parameter unit max. typ. min. t2
12 mb15e07 n phase comparator output waveform notes: 1. phase error detection range:? p to +2 p 2. pulses on do output signal during locked state are output to prevent dead zone. 3. ld output becomes low when phase is t wu or more. ld output becomes high when phase error is t wl or less and continues to be so for three cysles or more. 4. t wu and t wl depend on oscin input frequency. t wu 3 8/fosc (e g.t wu 3 625ns, foscin = 12.8 mhz) t wl 16/fosc (e g.t wl 1250ns, foscin = 12.8 mhz) 5. ld becomes high during the power saving mode (ps = ??) . fp fr ld [ fc = ??] f p f r do [ fc = ??] f p f r do h l z t wu t wl h l z
13 mb15e07 n test circuit (for measuring input sensitivity ?/oscin) p.g 50 w 1000pf 1000pf 0.1? 0.1? v cc v p 1000pf 50 w p.g 8 7 6 5 4 3 2 1 9 controller (setting devide ratio) v cc oscilloscope 10 11 12 13 14 15 16
14 mb15e07 n application example (continued) 16 15 14 13 12 11 10 9 mb15e07 12345678 1000pf 0.1 f c 1 x tal lpf vco osc in osc out v p v cc d o gnd xf in f in c 2 output from 12k w 12k w 10k w 10k w 0.1 f 1000pf to a lock detect. f r f p ld/f out zc ps le data clock c 1 , c 2 : depend on the crystal parameters
15 mb15e07 n typical characteristics (continued) do output current [ta = + 25?c] [v cc = 3 v, vp = 3 v, 5 v] 5.0 4.0 3.0 2.0 1.0 0 v oh (v) 0 ? ?0 ?5 ?0 i oh (ma) vp = 3 v vp = 5 v [ta = + 25?c] [v cc = 3 v, vp = 3 v, 5 v] 5.0 4.0 3.0 2.0 1.0 0 v ol (v) 0 5 10 15 20 i ol (ma) vp = 3 v vp = 5 v v cc = 2.7 v v cc = 3.0 v v cc = 3.6 v fin input sensitivity spec vfin vs. fin [ta = +25?c] +10 0 ?0 ?0 ?0 ?0 vfin (dbm) 0 1000 2000 3000 4000 fin (mhz) prescalar = 64/65 main. counter div. ratio = 4104 swallow = ?n v cc = vp
16 mb15e07 (continued) (continued) v cc = 2.7 v v cc = 3.0 v v cc = 3.6 v oscin input characteristics vf osc vs. f osc [ta = +25?c] +10 0 ?0 ?0 ?0 ?0 vf osc (dbm) 0 50 100 150 200 f osc (mhz) ref. counter div. ratio = 767 fin, xfin : open spec +10 0 ?0 ?0 ?0 ?0 spec vfin (dbm) 0 1000 2000 3000 fin (mhz) : vdd = 2.7 v : vdd = 3.0 v : vdd = 3.6 v prescaler = 32/33 main, counter div. ratio = 1860 swallow = ?n fin input snsitivity [ta = 25?c]
17 mb15e07 (continued) 4 : 39.314 w ?50.516 k w 3.2159 pf 1 : 10.188 w ?36.666 w 1 ghz 2 : 10.371 w 1.4438 w 1.5 ghz 3 : 16.474 w 31.454 w 2 ghz 2 500.000 000 mhz 1 3 4 3 : 030.13 w -2.389 k w 3.331 pf 1 : 3.516 w ?43.99 k w 1 mhz 2 : 150.5 w ?4.8388 k w 10 mhz 4 : 12.844 w ?948.37 w 50 mhz 20.000 000 mhz 1 3 4 2 2 oscin oscin input impedance fin fin input impedance
18 mb15e07 n reference information (continued) test circuit diagram (pcn application) -comparison freq ; 200 khz -r div ratio ; 65 -prescaler div ; 64/65 -fol = 1604 mhz -fom = 1642 mhz -foh = 1679 mhz 1 2 3 4 5 6 7 9 8 10 11 12 13 14 15 16 mb15e07 data interface board & pc f r f p ld fout zc ps 3.65 v le data clock 3.65 v 47 k 47 k 47 k f osc = 13 mhz oscin oscout vp v cc d o 0.1 m 0.1 m 10 m 10 m + + 51 100 pf signal generator hp8642b cox. vsupply = 3.65 v gnd xfin fin 1 n 1 k 33 n (film cap) 120 p 27 k 33 pf 1 nf -spectrum analyzer -time interval analyzer output cox. 18 18 18 nc gnd p kv = 43 mhz/v (mqe523-1619) b gnd c cox. v vco = 3.65 v 10 m + 0.1 m
19 mb15e07 pll lock up toem = 420 m s (1604 mhz ? 1679 mhz, within = 1khz) d mkr x : 420.01163 m s y : ?4.9991 mhz 30.00500 mhz 2.00 khz/div 29.99500 khz 5.1372 m s 1.9953872 m s pll lock up toem = 400 m s (1679 mhz ? 1604 mhz, within ? khz) d mkr x : 400.01227 m s y : ?5.0020 mhz 30.00500 mhz 2.00 khz/div 29.99500 khz 5.1366 m s 1.9953866 m s ref ?.2 dbm 10 db/ att 00 db mkr d ?00 khz ?0 db rbw 10 khz vbw 10 khz span 1.00 mhz center 1.67900 ghz pll reference leakage 200 mhz offset = ?0.0 dbc ref ?.7 dbm 10 db/ att 00 db mkr d 13.02 khz ?2.7 db rbw 300 khz vbw 300 khz span 60.0 mhz center 1.6420000 ghz pll phase noise @within loop band = ?7.5 dbc/hz (continued)
20 mb15e07 n ordering information part number package remarks MB15E07PFV1 16-pin plastic ssop (fpt-16p-m05)
21 mb15e07 n package dimension 16 pins, plastic ssop (fpt-16p-m05) * : these dimensions do not include resin protrusion. +0.20 C0.10 +.008 C.004 +0.10 C0.05 +.004 C.002 +0.05 C0.02 +.002 C.001 index "a" 0.10(.004) 1.25 .049 0.22 .009 0.15 .006 (.0256.0047) * (.173.004) (.252.008) nom 6.400.20 4.400.10 5.40(.213) 0.650.12 * 5.000.10(.197.004) 4.55(.179)ref details of "a" part 0 10 (stand off) 0.100.10(.004.004) (.020.008) 0.500.20 1994 fujitsu limited f16013s-2c-4 c dimensions in mm (inches)
24 fujitsu limited for further information please contact: japan fujitsu limited corporate global business support division electronic devices kawasaki plant, 4-1-1, kamikodanaka nakahara-ku, kawasaki-shi kanagawa 211-88, japan tel: (044) 754-3763 fax: (044) 754-3329 north and south america fujitsu microelectronics, inc. semiconductor division 3545 north first street san jose, ca 95134-1804, u.s.a. tel: (408) 922-9000 fax: (408) 432-9044/9045 europe fujitsu mikroelektronik gmbh am siebenstein 6-10 63303 dreieich-buchschlag germany tel: (06103) 690-0 fax: (06103) 690-122 asia paci? fujitsu microelectronics asia pte. limited #05-08, 151 lorong chuan new tech park singapore 556741 tel: (65) 281-0770 fax: (65) 281-0220 f9703 ? fujitsu limited printed in japan all rights reserved. the contents of this document are subject to change without notice. customers are advised to consult with fujitsu sales representatives before ordering. the information and circuit diagrams in this document presented as examples of semiconductor device applications, and are not intended to be incorporated in devices for actual use. also, fujitsu is unable to assume responsibility for infringement of any patent rights or other rights of third parties arising from the use of this information or circuit diagrams. fujitsu semiconductor devices are intended for use in standard applications (computers, office automation and other office equipment, industrial, communications, and measurement equipment, personal or household devices, etc.). caution: customers considering the use of our products in special applications where failure or abnormal operation may directly affect human lives or cause physical injury or property damage, or where extremely high levels of reliability are demanded (such as aerospace systems, atomic energy controls, sea floor repeaters, vehicle operating controls, medical devices for life support, etc.) are requested to consult with fujitsu sales representatives before such use. the company will not be responsible for damages arising from such use without prior approval. any semiconductor devices have inherently a certain rate of failure. you must protect against injury, damage or loss from such failures by incorporating safety design measures into your facility and equipment such as redundancy, fire protection, and prevention of over-current levels and other abnormal operating conditions. if any products described in this document represent goods or technologies subject to certain restrictions on export under the foreign exchange and foreign trade control law of japan, the prior authorization by japanese government should be required for export of those products from japan.

▲Up To Search▲

Price & Availability of MB15E07PFV1

	To Download MB15E07PFV1 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .